The present invention relates to a data transfer controller using a direct memory access (DMA) method and, more particularly, to a DMA controller for performing a data transfer between a memory and a peripheral unit.
In an information processing system employing a microcomputer, it is often necessary to transfer a number of data between a memory and a peripheral, unit. In such a case, if a central processing unit (CPU) is programmed to respond to an interrupt request from the peripheral unit and to then perform the data transfer in an interrupt program routine, an overhead of CPU, i.e. a time for interrupt processing, is increased resulting in lowering the data processing efficiency. Therefore, a DMA controller (DMAC) is proposed and employed as a data transfer controller for performing the data transfer in place of the CPU.
When the DMAC receives a DMA data transfer request from the peripheral unit such as a serial data communication control unit, a printer control unit, a display control unit and so forth, it requests a bus control right using address, data and control buses to CPU. In response to this request from the DMAC, the CPU suspends the program execution and then transfers the bus control right to the DMAC. The DMAC thereby performs the data transfer between the peripheral unit and the memory by use of the buses without intervention by the CPU. When a predetermined number of data are thus transferred between the peripheral unit and the memory by the DMA data transfer, the DMAC informs the CPU of the DMA transfer completion. When the CPU detects the DMA transfer completion, it either accesses the memory to read and process the data in the case of the DMA transfer from the peripheral unit to the memory, or it accesses the memory to write data to be transferred next in the case of the DMA transfer from the memory to the peripheral unit.
As a recent information processing system is demanded to further enhance the data processing efficiency and speed, the CPU is required to read and process the data transferred to the memory or to write new data into the memory at arbitrary timings without waiting for the DMA transfer completion information from the DMAC. To this end, the CPU has to detect not only the execution of the DMA data transfer but also the address of the memory to which the data from the peripheral unit has been transferred or the address of the data which has been transferred to the peripheral unit. That is, the CPU is required to monitor the execution state of the DMAC by a program. Hence, program overhead can be a serious problem.